MC9S12E256 Datasheet, PDF (147/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 3 Port Integration Module (PIM9E256V1)
3.3.5 Port S
Port S is associated with the serial peripheral interface (SPI) and serial communication interfaces (SCI0
and SCI1). Each pin is assigned to these modules according to the following priority: SPI/SCI1/SCI0 >
general-purpose I/O.
When the SPI is enabled, the PS[7:4] pins become SS, SCK, MOSI, and MISO respectively. Refer to
Chapter 9, “Serial Peripheral Interface (SPIV3)” for information on enabling and disabling the SPI.
When the SCI1 receiver and transmitter are enabled, the PS[3:2] pins become TXD1 and RXD1
respectively. When the SCI0 receiver and transmitter are enabled, the PS[1:0] pins become TXD0 and
RXD0 respectively. Refer to Chapter 8, “Serial Communication Interface (SCIV4)” for information on
enabling and disabling the SCI receiver and transmitter.
During reset, port S pins are configured as high-impedance inputs.
3.3.5.1 Port S I/O Register (PTS)
R
W
SPI:
SCI1/SCI0:
Reset
7
PTS7
SS
0
6
PTS6
5
PTS5
4
PTS4
3
PTS3
2
PTS2
SCK
MOSI
MISO
TXD1
RXD1
0
0
0
0
0
Figure 3-29. Port S I/O Register (PTS)
1
PTS1
TXD0
0
0
PTS0
RXD0
0
Read: Anytime. Write: Anytime.
If the associated data direction bit (DDRSx) is set to 1 (output), a read returns the value of the I/O register
bit. If the associated data direction bit (DDRSx) is set to 0 (input), a read returns the value of the pin.
3.3.5.2 Port S Input Register (PTIS)
7
R PTIS7
W
6
PTIS6
5
PTIS5
4
PTIS4
3
PTIS3
2
PTIS2
Reset
u
u
u
u
u
u
= Reserved or Unimplemented
u = Unaffected by reset
Figure 3-30. Port S Input Register (PTIS)
Read: Anytime. Write: Never, writes to this register have no effect.
This register always reads back the status of the associated pins.
1
PTIS1
u
0
PTIS0
u
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
147