MC9S12E256 Datasheet, PDF (355/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 11 Pulse Width Modulator with Fault Protection (PMF15B6CV2)
In an edge-aligned operation, the PWM counter is an up counter. The PWM output resolution is one bus
clock cycle.
PWM period = PWM modulus × PWM clock period
COUNT
1234
UP COUNTER
MODULUS = 4
PWM CLOCK PERIOD
PWM PERIOD = 4 x PWM CLOCK PERIOD
Figure 11-44. Edge-Aligned PWM Period
11.4.3.3 Duty Cycle
The signed 16-bit number written to the PMF value registers is the pulse width in PWM clock periods of
the PWM generator output.
Duty cycle
=
----P----M-----F----V-----A----L-----
MODULUS
×
100
NOTE
A PWM value less than or equal to zero deactivates the PWM output for the
entire PWM period. A PWM value greater than or equal to the modulus
activates the PWM output for the entire PWM period.
Table 11-46. PWM Value and Underflow Conditions
PMFVALx
$0000–$7FFF
$8000–$FFFF
Condition
Normal
Underflow
PWM Value Used
Value in registers
$0000
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
355