MC9S12E256 Datasheet, PDF (437/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 14
Dual Output Voltage Regulator (VREG3V3V2)
14.1 Introduction
The VREG is a dual output voltage regulator providing two separate 2.5 V (typical) supplies differing in
the amount of current that can be sourced. The regulator input voltage range is from 3.3 V up to 5 V
(typical).
14.1.1 Features
The block VREG includes these distinctive features:
• Two parallel, linear voltage regulators
— Bandgap reference
• Low-voltage detect (LVD) with low-voltage interrupt (LVI)
• Power-on reset (POR)
• Low-voltage reset (LVR)
14.1.2 Modes of Operation
There are three modes VREG can operate in:
• Full-performance mode (FPM) (MCU is not in stop mode)
The regulator is active, providing the nominal supply voltage of 2.5 V with full current sourcing
capability at both outputs. Features LVD (low-voltage detect), LVR (low-voltage reset), and POR
(power-on reset) are available.
• Reduced-power mode (RPM) (MCU is in stop mode)
The purpose is to reduce power consumption of the device. The output voltage may degrade to a
lower value than in full-performance mode, additionally the current sourcing capability is
substantially reduced. Only the POR is available in this mode, LVD and LVR are disabled.
• Shutdown mode
Controlled by V_REGEN (see Chapter 1, “MC9S12E256 Device Overview (MC9S12E256DGV1)”
for connectivity of V_REGEN).
This mode is characterized by minimum power consumption. The regulator outputs are in a high
impedance state, only the POR feature is available, LVD and LVR are disabled.
This mode must be used to disable the chip internal regulator VREG, i.e., to bypass the VREG to
use external supplies.
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
437