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MC9S12E256 Datasheet, PDF (445/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers
Chapter 15
Background Debug Module (BDMV4)
15.1 Introduction
This section describes the functionality of the background debug module (BDM) sub-block of the HCS12
core platform.
A block diagram of the BDM is shown in Figure 15-1.
HOST
SYSTEM
BKGD
16-BIT SHIFT REGISTER
ENTAG
BDMACT
TRACE
INSTRUCTION DECODE
AND EXECUTION
BUS INTERFACE
AND
CONTROL LOGIC
ADDRESS
DATA
CLOCKS
SDV
ENBDM
STANDARD BDM
FIRMWARE
LOOKUP TABLE
CLKSW
Figure 15-1. BDM Block Diagram
The background debug module (BDM) sub-block is a single-wire, background debug system implemented
in on-chip hardware for minimal CPU intervention. All interfacing with the BDM is done via the BKGD
pin.
BDMV4 has enhanced capability for maintaining synchronization between the target and host while
allowing more flexibility in clock rates. This includes a sync signal to show the clock rate and a handshake
signal to indicate when an operation is complete. The system is backwards compatible with older external
interfaces.
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
445