MC9S12E256 Datasheet, PDF (440/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 14 Dual Output Voltage Regulator (VREG3V3V2)
14.2.3 V_DD, V_SS — Regulator Output1 (Core Logic)
Signals V_DD/V_SS are the primary outputs of VREG that provide the power supply for the core logic. These
signals are connected to device pins to allow external decoupling capacitors (100 nF...220 nF, X7R
ceramic).
In shutdown mode an external supply at V_DD/V_SS can replace the voltage regulator.
14.2.4 V_DDPLL, V_SSPLL — Regulator Output2 (PLL)
Signals V_DDPLL/V_SSPLL are the secondary outputs of VREG that provide the power supply for the PLL
and oscillator. These signals are connected to device pins to allow external decoupling capacitors (100
nF...220 nF, X7R ceramic).
In shutdown mode an external supply at V_DDPLL/V_SSPLL can replace the voltage regulator.
14.2.5 V_REGEN — Optional Regulator Enable
This optional signal is used to shutdown VREG. In that case V_DD/V_SS and V_DDPLL/V_SSPLL must be
provided externally. shutdown mode is entered with V_REGEN being low. If V_REGEN is high, the VREG is
either in full-performance mode or in reduced-power mode.
For the connectivity of V_REGEN see Chapter 1, “MC9S12E256 Device Overview (MC9S12E256DGV1)”.
NOTE
Switching from FPM or RPM to shutdown of VREG and vice versa is not
supported while the MCU is powered.
14.3 Memory Map and Register Definition
This subsection provides a detailed description of all registers accessible in VREG.
14.3.1 Module Memory Map
Figure 14-2 provides an overview of all used registers.
Table 14-2. VREG Memory Map
Address
Offset
Use
0x0000 VREG Control Register (VREGCTRL)
Access
R/W
MC9S12E256 Data Sheet, Rev. 1.08
440
Freescale Semiconductor