MC9S12E256 Datasheet, PDF (431/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 13 Timer Module (TIM16B4CV1)
13.3.2.17 Pulse Accumulators Count Registers (PACNT)
15
R
PACNT15
W
14
PACNT14
13
PACNT13
12
PACNT12
11
PACNT11
10
PACNT10
9
PACNT9
Reset
0
0
0
0
0
0
0
Figure 13-24. Pulse Accumulator Count Register High (PACNTH)
0
PACNT8
0
R
W
Reset
7
PACNT7
0
6
PACNT6
5
PACNT5
4
PACNT4
3
PACNT3
2
PACNT2
1
PACNT1
0
0
0
0
0
0
Figure 13-25. Pulse Accumulator Count Register Low (PACNTL)
0
PACNT0
0
Read: Anytime
Write: Anytime
These registers contain the number of active input edges on its input pin since the last reset.
When PACNT overflows from 0xFFFF to 0x0000, the Interrupt flag PAOVF in PAFLG (0x0021) is set.
Full count register access should take place in one clock cycle. A separate read/write for high byte and low
byte will give a different result than accessing them as a word.
NOTE
Reading the pulse accumulator counter registers immediately after an
active edge on the pulse accumulator input pin may miss the last count
because the input has to be synchronized with the bus clock first.
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
431