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MC9S12E256 Datasheet, PDF (508/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers | |||
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Chapter 17 Interrupt (INTV1)
17.7 Exception Priority
The priority (from highest to lowest) and address of all exception vectors issued by the INT upon request
by the CPU is shown in Table 17-5.
Table 17-5. Exception Vector Map and Priority
Vector Address
0xFFFEâ0xFFFF
0xFFFCâ0xFFFD
0xFFFAâ0xFFFB
0xFFF8â0xFFF9
0xFFF6â0xFFF7
0xFFF4â0xFFF5
0xFFF2â0xFFF3
0xFFF0â0xFF00
Source
System reset
Crystal monitor reset
COP reset
Unimplemented opcode trap
Software interrupt instruction (SWI) or BDM vector request
XIRQ signal
IRQ signal
Device-specific I-bit maskable interrupt sources (priority in descending order)
MC9S12E256 Data Sheet, Rev. 1.08
508
Freescale Semiconductor
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