MC9S12E256 Datasheet, PDF (301/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Table 10-4. Multiplier Factor
IBC7-6
00
01
10
11
MUL
01
02
04
RESERVED
Chapter 10 Inter-Integrated Circuit (IICV2)
The number of clocks from the falling edge of SCL to the first tap (Tap[1]) is defined by the values shown
in the scl2tap column of Table 10-3, all subsequent tap points are separated by 2^IBC5-3 as shown in the
tap2tap column in Table 10-3. The SCL Tap is used to generated the SCL period and the SDA Tap is used
to determine the delay from the falling edge of SCL to SDA changing, the SDA hold time.
IBC7–6 defines the multiplier factor MUL. The values of MUL are shown in the Table 10-4.
SCL Divider
SCL
SDA
SDA Hold
SDA
SCL
SCL Hold(start)
SCL Hold(stop)
START condition
STOP condition
Figure 10-5. SCL Divider and SDA Hold
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
301