MC9S12E256 Datasheet, PDF (503/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

Chapter 17 Interrupt (INTV1)
17.2 External Signal Description
Most interfacing with the interrupt sub-block is done within the core. However, the interrupt does receive
direct input from the multiplexed external bus interface (MEBI) sub-block of the core for the IRQ and
XIRQ pin data.
17.3 Memory Map and Register Definition
Detailed descriptions of the registers and associated bits are given in the subsections that follow.
17.3.1 Module Memory Map
Table 17-1. INT Memory Map
Address
Offset
0x0015
0x0016
0x001F
Use
Interrupt Test Control Register (ITCR)
Interrupt Test Registers (ITEST)
Highest Priority Interrupt (Optional) (HPRIO)
Access
R/W
R/W
R/W
17.3.2 Register Descriptions
Address Name
0x0015
R
ITCR
W
0x0016
R
ITEST
W
0x001F
HPRIO ^R
(OPTIONAL) _W
Bit 7
0
INTE
PSEL7
6
5
4
3
2
0
0
WRTINT ADR3 ADR2
INTC
INTA
INT8
INT6
INT4
PSEL6 PSEL5 PSEL4 PSEL3 PSEL2
= Unimplemented or Reserved
Figure 17-2. INT Register Summary
1
ADR1
INT2
PSEL1
Bit 0
ADR0
INT0
0
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
503