MC9S12E256 Datasheet, PDF (429/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

PAMOD
0
0
1
1
PEDGE
0
1
0
1
Chapter 13 Timer Module (TIM16B4CV1)
Table 13-18. Pin Action
Pin Action
Falling edge
Rising edge
Div. by 64 clock enabled with pin high level
Div. by 64 clock enabled with pin low level
NOTE
If the timer is not active (TEN = 0 in TSCR), there is no divide-by-64
because the ÷64 clock is generated by the timer prescaler.
CLK1
0
0
1
1
Table 13-19. Timer Clock Selection
CLK0
0
1
0
1
Timer Clock
Use timer prescaler clock as timer counter clock
Use PACLK as input to timer counter clock
Use PACLK/256 as timer counter clock frequency
Use PACLK/65536 as timer counter clock frequency
For the description of PACLK please refer Figure 13-22.
If the pulse accumulator is disabled (PAEN = 0), the prescaler clock from the timer is always used as an
input clock to the timer counter. The change from one selected clock to the other happens immediately
after these bits are written.
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
429