MC9S12E256 Datasheet, PDF (131/602 Pages) Freescale Semiconductor, Inc – HCS12 Microcontrollers

3.3.1.2 Port AD Input Register (PTIAD)
Chapter 3 Port Integration Module (PIM9E256V1)
R
W
Reset
7
PTIAD15
1
6
PTIAD14
1
5
PTIAD13
1
4
PTIAD12
1
3
PTIAD11
1
2
PTIAD10
1
R
W
Reset
7
PTIAD7
1
6
PTIAD6
5
PTIAD5
4
PTIAD4
1
1
1
= Reserved or Unimplemented
3
PTIAD3
1
2
PTIAD2
1
Figure 3-3. Port AD Input Register (PTIAD)
1
PTIAD9
1
1
PTIAD1
1
0
PTIAD8
1
0
PTIAD0
1
Read: Anytime. Write: Never; writes to these registers have no effect.
If the ATDDIEN0(1) bit of the associated I/O pin is set to 0 (digital input buffer is disabled), a read returns
a 1. If the ATDDIEN0(1) bit of the associated I/O pin is set to 1 (digital input buffer is enabled), a read
returns the status of the associated pin.
3.3.1.3 Port AD Data Direction Register (DDRAD)
7
R
DDRAD15
W
Reset
0
R
W
Reset
7
DDRAD7
0
6
DDRAD14
5
DDRAD13
4
DDRAD12
3
DDRAD11
2
DDRAD10
0
6
DDRAD6
0
5
DDRAD5
0
4
DDRAD4
0
3
DDRAD3
0
2
DDRAD2
0
0
0
0
0
Figure 3-4. Port AD Data Direction Register (DDRAD)
1
DDRAD9
0
1
DDRAD1
0
0
DDRAD8
0
0
DDRAD0
0
Read: Anytime. Write: Anytime.
This register configures port pins PAD[15:0] as either input or output.
If a data direction bit is 0 (pin configured as input), then a read value on PTADx depends on the associated
ATDDIEN0(1) bit. If the associated ATDDIEN0(1) bit is set to 1 (digital input buffer is enabled), a read
on PTADx returns the value on port AD pin. If the associated ATDDIEN0(1) bit is set to 0 (digital input
buffer is disabled), a read on PTADx returns a 1.
Table 3-3. DDRAD Field Descriptions
Field
15:0
Data Direction Port AD
DDRAD[15:0] 0 Associated pin is configured as input.
1 Associated pin is configured as output.
Description
MC9S12E256 Data Sheet, Rev. 1.08
Freescale Semiconductor
131