MC68HC908LJ24 Datasheet, PDF (81/464 Pages) Motorola, Inc – Microcontrollers

Configuration Registers (CONFIG)
Configuration Register 1 (CONFIG1)
5.4 Configuration Register 1 (CONFIG1)
The CONFIG1 register can be written once after each reset.
Address: $001F
Bit 7
6
5
4
3
Read:
0
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
Reset: 0
0
0
0^††
0
†† Reset by POR only.
= Unimplemented
2
1
SSREC STOP
0
0
Figure 5-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS. (See
Section 21. Computer Operating Properly (COP).)
1 = COP time out period = 2¹³ – 2⁴ ICLK cycles
0 = COP time out period = 2¹⁸ – 2⁴ ICLK cycles
LVISTOP — LVI Enable in Stop Mode
When the LVIPWRD bit is clear, setting the LVISTOP bit enables the
LVI to operate during stop mode. Reset clears LVISTOP. (See
Section 22. Low-Voltage Inhibit (LVI).)
1 = LVI enabled during stop mode
0 = LVI disabled during stop mode
LVIRSTD — LVI Reset Disable
LVIRSTD disables the reset signal from the LVI module. (See
Section 22. Low-Voltage Inhibit (LVI).)
1 = LVI module resets disabled
0 = LVI module resets enabled
LVIPWRD — LVI Power Disable Bit
LVIPWRD disables the LVI module. (See Section 22. Low-Voltage
Inhibit (LVI).)
1 = LVI module power disabled
0 = LVI module power enabled
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Configuration Registers (CONFIG)
Data Sheet
81