MC68HC908LJ24 Datasheet, PDF (158/464 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin OR CPU interrupt OR break interrupt
Figure 9-16. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
CYCLES
32
CYCLES
RSTVCTH RSTVCTL
IDB $A6 $A6
$A6
RST
ICLK
Figure 9-17. Wait Recovery from Internal Reset
9.7.2 Stop Mode
In stop mode, the SIM counter is reset and the system clocks are
disabled. An interrupt request from a module can cause an exit from stop
mode. Stacking for interrupts begins after the selected stop recovery
time has elapsed. Reset or break also causes an exit from stop mode.
The SIM disables the clock generator module output (CGMOUT) in stop
mode, stopping the CPU and peripherals. Stop recovery time is
selectable using the SSREC bit in the configuration register 1
(CONFIG1). If SSREC is set, stop recovery is reduced from the normal
delay of 4096 ICLK cycles down to 32. This is ideal for applications using
canned oscillators that do not require long start-up times from stop
mode.
NOTE: External crystal applications should use the full stop recovery time by
clearing the SSREC bit.
Data Sheet
158
System Integration Module (SIM)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor