MC68HC908LJ24 Datasheet, PDF (418/464 Pages) Motorola, Inc – Microcontrollers

Computer Operating Properly (COP)
21.4.5 Internal Reset
An internal reset clears the COP prescaler and the COP counter.
21.4.6 Reset Vector Fetch
A reset vector fetch occurs when the vector address appears on the data
bus. A reset vector fetch clears the COP prescaler.
21.4.7 COPD (COP Disable)
The COPD signal reflects the state of the COP disable bit (COPD) in the
CONFIG1 register. (See Figure 21-2 and Section 5. Configuration
Registers (CONFIG).)
21.4.8 COPRS (COP Rate Select)
The COPRS signal reflects the state of the COP rate select bit (COPRS)
in the CONFIG1 register.
Address: $001F
Bit 7
6
5
4
3
2
1
Read:
0
COPRS LVISTOP LVIRSTD LVIPWRD
Write:
Reset: 0
0
0
0^††
0
SSREC STOP
0
0
†† Reset by POR only.
= Unimplemented
Figure 21-2. Configuration Register 1 (CONFIG1)
Bit 0
COPD
0
COPRS — COP Rate Select
COPRS selects the COP time-out period. Reset clears COPRS.
1 = COP time out period = 2¹³ – 2⁴ ICLK cycles
0 = COP time out period = 2¹⁸ – 2⁴ ICLK cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
Data Sheet
418
MC68HC908LJ24/LK24 — Rev. 2.1
Computer Operating Properly (COP)
Freescale Semiconductor