MC68HC908LJ24 Datasheet, PDF (141/464 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Introduction
STOP/WAIT
CONTROL
SIM
COUNTER
÷2
MODULE STOP
MODULE WAIT
CPU STOP (FROM CPU)
CPU WAIT (FROM CPU)
SIMOSCEN (TO CGM, OSC)
COP CLOCK
ICLK (FROM OSC)
CGMOUT (FROM CGM)
RESET
PIN LOGIC
V_DD
INTERNAL
PULLUP
DEVICE
CLOCK
CONTROL
CLOCK GENERATORS
POR CONTROL
RESET PIN CONTROL
SIM RESET STATUS REGISTER
MASTER
RESET
CONTROL
RESET
INTERNAL CLOCKS
LVI (FROM LVI MODULE)
ILLEGAL OPCODE (FROM CPU)
ILLEGAL ADDRESS
(FROM ADDRESS MAP DECODERS)
COP (FROM COP MODULE)
Signal Name
ICLK
CGMXCLK
CGMPCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
INTERRUPT CONTROL
AND PRIORITY DECODE
INTERRUPT SOURCES
CPU INTERFACE
Figure 9-1. SIM Block Diagram
Table 9-1. Signal Name Conventions
Description
Internal RC oscillator clock
Buffered version of OSC1 from the oscillator module
The divided PLL output
PLL-based or oscillator-based clock output from CGM module
(Bus clock = CGMOUT ÷ 2)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
System Integration Module (SIM)
Data Sheet
141