MC68HC908LJ24 Datasheet, PDF (385/464 Pages) Motorola, Inc – Microcontrollers

Input/Output (I/O) Ports
Port B
18.4.2 Data Direction Register B (DDRB)
Data direction register B determines whether each port B pin is an input
or an output. Writing a logic 1 to a DDRB bit enables the output buffer for
the corresponding port B pin; a logic 0 disables the output buffer.
Address: $0005
Bit 7
6
5
4
3
2
1
Read:
DDRB7
Write:
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
Reset: 0
0
0
0
0
0
0
Figure 18-6. Data Direction Register B (DDRB)
Bit 0
DDRB0
0
DDRB[7:0] — Data Direction Register B Bits
These read/write bits control port B data direction. Reset clears
DDRB[7:0], configuring all port B pins as inputs.
1 = Corresponding port B pin configured as output
0 = Corresponding port B pin configured as input
NOTE:
Avoid glitches on port B pins by writing to the port B data register before
changing data direction register B bits from 0 to 1. Figure 18-7 shows
the port B I/O logic.
READ DDRB ($0005)
WRITE DDRB ($0005)
RESET
WRITE PTB ($0001)
DDRBx
PTBx
PTBx
READ PTB ($0001)
Figure 18-7. Port B I/O Circuit
When DDRBx is a logic 1, reading address $0001 reads the PTBx data
latch. When DDRBx is a logic 0, reading address $0001 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Input/Output (I/O) Ports
Data Sheet
385