MC68HC908LJ24 Datasheet, PDF (416/464 Pages) Motorola, Inc – Microcontrollers

Computer Operating Properly (COP)
21.3 Functional Description
Figure 21-1 shows the structure of the COP module.
ICLK
12-BIT COP PRESCALER
RESET CIRCUIT
RESET STATUS REGISTER
STOP INSTRUCTION
INTERNAL RESET SOURCES
RESET VECTOR FETCH
COPCTL WRITE
COP CLOCK
COPEN (FROM SIM)
COP DISABLE
(COPD FROM CONFIG1)
RESET
COPCTL WRITE
COP RATE SEL
(COPRS FROM CONFIG1)
6-BIT COP COUNTER
CLEAR
COP COUNTER
Figure 21-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
prescaler counter. If not cleared by software, the COP counter overflows
and generates an asynchronous reset after 2¹⁸ – 2⁴ or 2¹³ – 2⁴ ICLK
cycles, depending on the state of the COP rate select bit, COPRS, in the
CONFIG1 register. With a 2¹³ – 2⁴ ICLK cycle overflow option, a 47-kHz
ICLK gives a COP timeout period of 174ms. Writing any value to location
$FFFF before an overflow occurs prevents a COP reset by clearing the
COP counter and stages 12 through 5 of the prescaler.
NOTE:
Service the COP immediately after reset and before entering or after
exiting STOP Mode to guarantee the maximum time before the first COP
counter overflow.
Data Sheet
416
MC68HC908LJ24/LK24 — Rev. 2.1
Computer Operating Properly (COP)
Freescale Semiconductor