MC68HC908LJ24 Datasheet, PDF (382/464 Pages) Motorola, Inc – Microcontrollers

Input/Output (I/O) Ports
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
READ PTA ($0000)
DDRAx
PTAx
PTAx
Figure 18-4. Port A I/O Circuit
When DDRAx is a logic 1, reading address $0000 reads the PTAx data
latch. When DDRAx is a logic 0, reading address $0000 reads the
voltage level on the pin. The data latch can always be written, regardless
of the state of its data direction bit.
Table 18-2 summarizes the operation of the port A pins.
Table 18-2. Port A Pin Functions
DDRA
Bit
0
PTA Bit
X⁽¹⁾
I/O Pin Mode
Input, Hi-Z⁽²⁾
Accesses to DDRA
Read/Write
DDRA[7:0]
1
X
Output
DDRA[7:0]
Notes:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
Accesses to PTA
Read
Pin
Write
PTA[7:0]⁽³⁾
PTA[7:0] PTA[7:0]
Data Sheet
382
Input/Output (I/O) Ports
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor