MC68HC908LJ24 Datasheet, PDF (425/464 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
LVI Status Register
22.4.4 LVI Trip Selection
The trip point selection bits, LVISEL[1:0], in the CONFIG2 register select
whether the LVI is configured for 5V or 3 V operation. (See Section 5.
Configuration Registers (CONFIG).)
NOTE:
The MCU is guaranteed to operate at a minimum supply voltage. The trip
point (V_TRIPF [5V] or V_TRIPF [3V]) may be lower than this. (See
Section 24. Electrical Specifications for the actual trip point voltages.)
22.5 LVI Status Register
The LVI status register (LVISR) controls LVI interrupt functions and
indicates if the V_DD voltage was detected below the V_TRIPF level.
Address: $FE0F
Bit 7
6
5
4
3
2
1
Bit 0
Read: LVIOUT
LVIIF
0
0
0
0
0
LVIIE
Write:
LVIIACK
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Table 22-1. LVI Status Register (LVISR)
LVIOUT — LVI Output Bit
This read-only flag becomes set when the V_DD voltage falls below the
V_TRIPF trip voltage (see Table 22-2). Reset clears the LVIOUT bit.
Table 22-2. LVIOUT Bit Indication
V_DD
V_DD > V_TRIPR
V_DD < V_TRIPF
V_TRIPF < V_DD < V_TRIPR
LVIOUT
0
1
Previous value
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Low-Voltage Inhibit (LVI)
Data Sheet
425