MC68HC908LJ24 Datasheet, PDF (335/464 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
Functional Descriptions
Addr.
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Register Name
ADC Status and Control ^Read:
Register Write:
(ADSCR) _Reset:
Read:
ADC Data Register High
(ADRH)
Write:
Reset:
ADC Data Register Low ^Read:
(ADRL) Write:
Reset:
ADC Clock Register ^Read:
(ADCLK) Write:
Reset:
Bit 7
COCO
0
ADx
R
0
ADx
R
0
ADIV2
0
6
5
AIEN ADCO
0
0
ADx
ADx
R
R
0
0
ADx
ADx
R
R
0
0
ADIV1 ADIV0
0
0
= Unimplemented
4
3
2
1
ADCH4 ADCH3 ADCH2 ADCH1
1
1
1
1
ADx
ADx
ADx
ADx
R
R
R
R
0
0
0
0
ADx
ADx
ADx
ADx
R
R
R
R
0
0
0
0
0
ADICLK MODE1 MODE0
0
0
1
0
R = Reserved
Bit 0
ADCH0
1
ADx
R
0
ADx
R
0
0
R
0
Figure 16-1. ADC I/O Register Summary
16.4 Functional Descriptions
The ADC provides six pins for sampling external sources at pins
PTA4/ADC0–PTA7/ADC3 and PTB6/ADC4–PTB7/ADC5. An analog
multiplexer allows the single ADC converter to select one of ten ADC
channels as ADC voltage in (V_ADIN). V_ADIN is converted by the
successive approximation register-based analog-to-digital converter.
When the conversion is completed, ADC places the result in the ADC
data register, high and low byte (ADRH and ADRL), and sets a flag or
generates an interrupt.
Figure 16-2 shows the structure of the ADC module.
16.4.1 ADC Port I/O Pins
PTA4–PTA7 and PTB6–PTB7 are general-purpose I/O pins that are
shared with the ADC channels. The channel select bits, ADCH[4:0],
define which ADC channel/port pin will be used as the input signal. The
ADC overrides the port I/O logic by forcing that pin as input to the ADC.
The remaining ADC channels/port pins are controlled by the port I/O
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Data Sheet
335