MC68HC908LJ24 Datasheet, PDF (324/464 Pages) Motorola, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
REPSEN — Repeated Start Enable
This bit is set to enable repeated START signal to be generated when
in master mode transfer (MMAST = 1). The REPSEN bit is cleared by
hardware after the completion of repeated START signal or when the
MMAST bit is cleared. Reset clears this bit.
1 = Repeated START signal will be generated if MMAST bit is set
0 = No repeated START signal will be generated
15.5.3 Multi-Master IIC Master Control Register (MIMCR)
Address: $006A
Bit 7
6
5
Read: MMALIF MMNAKIF MMBB
Write: 0
0
4
MMAST
3
MMRW
2
1
Bit 0
MMBR2 MMBR1 MMBR0
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 15-4. Multi-Master IIC Master Control Register (MIMCR)
MMALIF — Multi-Master Arbitration Lost Interrupt Flag
This flag is set when software attempt to set MMAST but the MMBB
has been set by detecting the start condition on the lines or when the
MMIIC is transmitting a "1" to SDA line but detected a "0" from SDA
line in master mode – an arbitration loss. This bit generates an
interrupt request to the CPU if the MMIEN bit in MMCR is also set.
This bit is cleared by writing "0" to it or by reset.
1 = Lost arbitration in master mode
0 = No arbitration lost
MMNAKIF — No Acknowledge Interrupt Flag
This flag is only set in master mode (MMAST = 1) when there is no
acknowledge bit detected after one data byte or calling address is
transferred. This flag also clears MMAST. MMNAKIF generates an
interrupt request to CPU if the MMIEN bit in MMCR is also set. This
bit is cleared by writing "0" to it or by reset.
1 = No acknowledge bit detected
0 = Acknowledge bit detected
Data Sheet
324
MC68HC908LJ24/LK24 — Rev. 2.1
Multi-Master IIC Interface (MMIIC)
Freescale Semiconductor