MC68HC908LJ24 Datasheet, PDF (356/464 Pages) Motorola, Inc – Microcontrollers

Liquid Crystal Display (LCD) Driver
The LCD cycle frame is determined by the equation:
1
LCD CYCLE FRAME =
LCD WAVEFORM BASE CLOCK × DUTY
For example, for 1/3 duty and 256Hz waveform base clock:
1
LCD CYCLE FRAME =
256 × (1/3)
= 11.72 ms
17.5.4 Fast Charge and Low Current
The default value for each of the bias resistors (see Figure 17-3), R_LCD,
in the resistor ladder is approximately 37kΩ at V_LCD = 3V. The relatively
high current drain through the 37kΩ resistor ladder may not be suitable
for some LCD panel connections. Lowering this current is possible by
setting the LC bit in the LCD control register, switching the R_LCD value
to 146kΩ.
Although the lower current drain is desirable, but in some LCD panel
connections, the higher current is required to drive the capacitive load of
the LCD panel. In most cases, the higher current is only required when
the LCD waveforms change state (the rising and falling edges in the LCD
output waveforms). The fast charge option is designed to have the high
current for the switching and the low current for the steady state. Setting
the FC bit in the LCD control register selects the fast charge option. The
R_LCD value is set to 37kΩ (for high current) for a fraction of time for each
LCD waveform switching edge, and then back to 146kΩ for the steady
state period. The duration of the fast charge time is set by configuring the
FCCTL[1:0] bits in the LCD clock register, and can be LCDCLK/32,
LCDCLK/64, or LCDCLK/128. Figure 17-4 shows the fast charge clock
relative to the BP0 waveform.
Data Sheet
356
MC68HC908LJ24/LK24 — Rev. 2.1
Liquid Crystal Display (LCD) Driver
Freescale Semiconductor