MC68HC908LJ24 Datasheet, PDF (326/464 Pages) Motorola, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
MMBR2
0
0
0
0
1
1
1
1
Table 15-2. Baud Rate Select
MMBR1
0
0
1
1
0
0
1
1
MMBR0
0
1
0
1
0
1
0
1
Baud Rate
Internal bus clock ÷ 8
Internal bus clock ÷ 16
Internal bus clock ÷ 32
Internal bus clock ÷ 64
Internal bus clock ÷ 128
Internal bus clock ÷ 256
Internal bus clock ÷ 512
Internal bus clock ÷ 1024
15.5.4 Multi-Master IIC Status Register (MMSR)
Address: $006D
Bit 7
6
5
4
3
2
1
Bit 0
Read: MMRXIF MMTXIF MMATCH MMSRW MMRXAK 0 MMTXBE MMRXBF
Write: 0
0
Reset: 0
0
0
0
1
0
1
0
= Unimplemented
Figure 15-5. Multi-Master IIC Status Register (MMSR)
MMRXIF — Multi-Master IIC Receive Interrupt Flag
This flag is set after the data receive register (MMDRR) is loaded with
a new received data. Once the MMDRR is loaded with received data,
no more received data can be loaded to the MMDRR register until the
CPU reads the data from the MMDRR to clear MMRXBF flag.
MMRXIF generates an interrupt request to CPU if the MMIEN bit in
MMCR is also set. This bit is cleared by writing "0" to it or by reset; or
when the MMEN = 0.
1 = New data in data receive register (MMDRR)
0 = No data received
Data Sheet
326
MC68HC908LJ24/LK24 — Rev. 2.1
Multi-Master IIC Interface (MMIIC)
Freescale Semiconductor