MC68HC908LJ24 Datasheet, PDF (153/464 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
Exception Control
9.6.1.2 SWI Instruction
The SWI instruction is a non-maskable instruction that causes an
interrupt regardless of the state of the interrupt mask (I bit) in the
condition code register.
NOTE: A software interrupt pushes PC onto the stack. A software interrupt does
not push PC – 1, as a hardware interrupt does.
9.6.1.3 Interrupt Status Registers
The flags in the interrupt status registers identify maskable interrupt
sources. Table 9-3 summarizes the interrupt sources and the interrupt
status register flags that they set. The interrupt status registers can be
useful for debugging.
9.6.1.4 Interrupt Status Register 1
Address: $FE04
Bit 7
6
5
4
3
2
Read: IF6
IF5
IF4
IF3
IF2
IF1
Write: R
R
R
R
R
R
Reset: 0
0
0
0
0
0
R = Reserved
1
Bit 0
0
0
R
R
0
0
Figure 9-12. Interrupt Status Register 1 (INT1)
IF6–IF1 — Interrupt Flags 6–1
These flags indicate the presence of interrupt requests from the
sources shown in Table 9-3.
1 = Interrupt request present
0 = No interrupt request present
Bit 0 and Bit 1 — Always read 0
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
System Integration Module (SIM)
Data Sheet
153