MC68HC908LJ24 Datasheet, PDF (344/464 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
16.8.2 ADC Data Register
The ADC data register consist of a pair of 8-bit registers: high byte
(ADRH), and low byte (ADRL). This pair form a 16-bit register to store
the 10-bit ADC result for the selected ADC result justification mode.
In 8-bit truncated mode, the ADRL holds the eight most significant bits
(MSBs) of the 10-bit result. The ADRL is updated each time an ADC
conversion completes. In 8-bit truncated mode, ADRL contains no
interlocking with ADRH. (See Figure 16-5 . ADRH and ADRL in 8-Bit
Truncated Mode.)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
0
0
$003D
ADC Data Register High
(ADRH)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
$003E
ADC Data Register Low
(ADRL)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Figure 16-5. ADRH and ADRL in 8-Bit Truncated Mode
In right justified mode the ADRH holds the two MSBs, and the ADRL
holds the eight least significant bits (LSBs), of the 10-bit result. ADRH
and ADRL are updated each time a single channel ADC conversion
completes. Reading ADRH latches the contents of ADRL. Until ADRL is
read all subsequent ADC results will be lost.
(See Figure 16-6 . ADRH and ADRL in Right Justified Mode.)
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
AD9
AD8
$003D
ADC Data Register High
(ADRH)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Read: AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
$003E
ADC Data Register Low
(ADRL)
Write:
R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
Figure 16-6. ADRH and ADRL in Right Justified Mode
Data Sheet
344
Analog-to-Digital Converter (ADC)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor