MC68HC908LJ24 Datasheet, PDF (321/464 Pages) Motorola, Inc – Microcontrollers

Multi-Master IIC Interface (MMIIC)
Multi-Master IIC Registers
Addr.
$006A
$006B
$006C
$006D
$006E
$006F
Register Name
Bit 7
6
5
Multi-Master IIC ^Read:
Master Control Register Write:
(MIMCR) _Reset:
MMALIF
0
0
MMNAKIF
0
0
MMBB
0
Multi-Master IIC Address
Register
Read:
Write:
MMAD7
(MMADR) _{Reset: 1}
MMAD6
0
MMAD5
1
Multi-Master IIC Control ^Read: _{MMEN MMIEN}
0
Register Write:
(MMCR) _{Reset: 0}
0
0
Multi-Master IIC ^{Read: MMRXIF}
Status Register Write: 0
(MMSR) _{Reset: 0}
MMTXIF MMATCH
0
0
0
Multi-Master IIC ^Read: _MMTD7
Data Transmit Register Write:
(MMDTR) _{Reset: 1}
MMTD6
1
MMTD5
1
Multi-Master IIC Read: MMRD7
Data Receive Register
(MMDRR)
Write:
Reset: 0
MMRD6
0
MMRD5
0
= Unimplemented
4
MMAST
0
MMAD4
0
0
0
MMSRW
0
MMTD4
1
MMRD4
0
3
MMRW
0
MMAD3
0
MMTXAK
0
MMRXAK
1
MMTD3
1
MMRD3
0
2
MMBR2
0
MMAD2
0
REPSEN
0
0
0
MMTD2
1
MMRD2
0
1
Bit 0
MMBR1 MMBR0
0
0
MMAD1 MMEXTAD
0
0
0
0
0
0
MMTXBE MMRXBF
1
0
MMTD1 MMTD0
1
1
MMRD1 MMRD0
0
0
Figure 15-1. MMIIC I/O Register Summary
15.5 Multi-Master IIC Registers
Six registers are associated with the Multi-master IIC module, they are
outlined in the following sections.
15.5.1 Multi-Master IIC Address Register (MMADR)
Address: $006B
Bit 7
6
5
4
3
2
1
Bit 0
Read:
MMAD7 MMAD6 MMAD5 MMAD4 MMAD3 MMAD2 MMAD1 MMEXTAD
Write:
Reset: 1
0
1
0
0
0
0
0
Figure 15-2. Multi-Master IIC Address Register (MMADR)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Multi-Master IIC Interface (MMIIC)
Data Sheet
321