MC68HC908LJ24 Datasheet, PDF (131/464 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
CGM Registers
8.6.4 PLL VCO Range Select Register
The PLL VCO range select register (PMRS) contains the programming
information required for the hardware configuration of the VCO.
Address: $003A
Bit 7
6
5
4
3
2
1
Read:
VRS7
Write:
VRS6
VRS5
VRS4
VRS3
VRS2
VRS1
Reset: 0
1
0
0
0
0
0
Figure 8-8. PLL VCO Range Select Register (PMRS)
Bit 0
VRS0
0
VRS[7:0] — VCO Range Select Bits
These read/write bits control the hardware center-of-range linear
multiplier L which, in conjunction with E (See 8.4.3 PLL Circuits,
8.4.6 Programming the PLL, and 8.6.1 PLL Control Register.),
controls the hardware center-of-range frequency, f_VRS. VRS[7:0]
cannot be written when the PLLON bit in the PCTL is set. (See 8.4.7
Special Programming Exceptions.) A value of $00 in the VCO
range select register disables the PLL and clears the BCS bit in the
PLL control register (PCTL). (See 8.4.8 Base Clock Selector Circuit
and 8.4.7 Special Programming Exceptions.). Reset initializes the
register to $40 for a default range multiply value of 64.
NOTE:
The VCO range select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1) and such that the VCO clock
cannot be selected as the source of the base clock (BCS = 1) if the VCO
range select bits are all clear.
The PLL VCO range select register must be programmed correctly.
Incorrect programming can result in failure of the PLL to achieve lock.
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Clock Generator Module (CGM)
Data Sheet
131