MC68HC908LJ24 Datasheet, PDF (130/464 Pages) Motorola, Inc – Microcontrollers

Clock Generator Module (CGM)
8.6.3 PLL Multiplier Select Registers
The PLL multiplier select registers (PMSH and PMSL) contain the
programming information for the modulo feedback divider.
Address: $0038
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
MUL11 MUL10 MUL9 MUL8
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 8-6. PLL Multiplier Select Register High (PMSH)
Address:
Read:
Write:
Reset:
$0039
Bit 7
MUL7
0
6
MUL6
1
5
MUL5
0
4
MUL4
0
3
MUL3
0
2
MUL2
0
1
MUL1
0
Bit 0
MUL0
0
Figure 8-7. PLL Multiplier Select Register Low (PMSL)
MUL[11:0] — Multiplier Select Bits
These read/write bits control the modulo feedback divider that selects
the VCO frequency multiplier N. (See 8.4.3 PLL Circuits and 8.4.6
Programming the PLL.) A value of $0000 in the multiplier select
registers configure the modulo feedback divider the same as a value
of $0001. Reset initializes the registers to $0040 for a default multiply
value of 64.
NOTE: The multiplier select bits have built-in protection such that they cannot
be written when the PLL is on (PLLON = 1).
Data Sheet
130
Clock Generator Module (CGM)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor