MC68HC908LJ24 Datasheet, PDF (279/464 Pages) Motorola, Inc – Microcontrollers

Infrared Serial Communications Interface Module (IRSCI)
I/O Registers
NORMAL FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 2
BYTE 3
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 3
BYTE 4
DELAYED FLAG CLEARING SEQUENCE
BYTE 1
BYTE 2
READ SCS1
SCRF = 1
OR = 0
READ SCDR
BYTE 1
BYTE 3
READ SCS1
SCRF = 1
OR = 1
READ SCDR
BYTE 3
BYTE 4
Figure 13-16. Flag Clearing Sequence
PE — Receiver Parity Error Bit
This clearable, read-only bit is set when the SCI detects a parity error
in incoming data. PE generates an SCI error CPU interrupt request if
the PEIE bit in SCC3 is also set. Clear the PE bit by reading SCS1
with PE set and then reading the SCDR. Reset clears the PE bit.
1 = Parity error detected
0 = No parity error detected
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor Infrared Serial Communications Interface Module (IRSCI)
Data Sheet
279