MC68HC908LJ24 Datasheet, PDF (347/464 Pages) Motorola, Inc – Microcontrollers

Analog-to-Digital Converter (ADC)
I/O Registers
If the external clock (CGMXCLK) is equal to or greater than 1MHz,
CGMXCLK can be used as the clock source for the ADC. If
CGMXCLK is less than 1MHz, use the PLL-generated bus clock as
the clock source. As long as the internal ADC clock is at f_ADIC, correct
operation can be guaranteed.
1 = Internal bus clock
0 = External clock, CGMXCLK
f_ADIC =
CGMXCLK or bus frequency
ADIV[2:0]
MODE1 and MODE0 — Modes of Result Justification
MODE1 and MODE0 selects between four modes of operation. The
manner in which the ADC conversion results will be placed in the ADC
data registers is controlled by these modes of operation. Reset
returns right-justified mode.
Table 16-3. ADC Mode Select
MODE1
0
0
1
1
MODE0
0
1
0
1
ADC Clock Rate
8-bit truncated mode
Right justified mode
Left justified mode
Left justified sign data mode
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
Analog-to-Digital Converter (ADC)
Data Sheet
347