MC68HC908LJ24 Datasheet, PDF (426/464 Pages) Motorola, Inc – Microcontrollers

Low-Voltage Inhibit (LVI)
LVIIE — LVI Interrupt Enable Bit
This read/write bit enables the LVIIF bit to generate CPU interrupt
requests. Reset clears the LVIIE bit.
1 = LVIIF can generate CPU interrupt requests
0 = LVIIF cannot generate CPU interrupt requests
LVIIF — LVI Interrupt Flag
This clearable, read-only flag is set whenever the LVIOUT bit toggles.
Reset clears the LVIIF bit.
1 = LVIOUT has toggled
0 = LVIOUT has not toggled
LVIIACK — LVI Interrupt Acknowledge Bit
Writing a logic 1 to this write-only bit clears the LVI interrupt flag,
LVIIF. LVIIACK always reads as logic 0.
1 = Clears LVIIF bit
0 = No effect
22.6 Low-Power Modes
The STOP and WAIT instructions put the MCU in low power-
consumption standby modes.
22.6.1 Wait Mode
If enabled, the LVI module remains active in wait mode. If enabled to
generate resets or interrupts, the LVI module can generate a reset or an
interrupt and bring the MCU out of wait mode.
22.6.2 Stop Mode
If enabled in stop mode (LVISTOP = 1), the LVI module remains active
in stop mode. If enabled to generate resets or interrupts, the LVI module
can generate a reset or an interrupt and bring the MCU out of stop mode.
NOTE: If enabled to generate both resets and interrupts, there will be no LVI
interrupts, as resets have a higher priority.
Data Sheet
426
Low-Voltage Inhibit (LVI)
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor