MC68HC908LJ24 Datasheet, PDF (143/464 Pages) Motorola, Inc – Microcontrollers

System Integration Module (SIM)
SIM Bus Clock Control and Generation
OSC2
OSC1
OSCILLATOR (OSC) MODULE
CGMXCLK
TO RTC, ADC
STOP MODE CLOCK
ENABLE SIGNALS
FROM CONFIG2
CGMRCLK
PHASE-LOCKED LOOP (PLL)
ICLK
CGMOUT
SIM COUNTER
SYSTEM INTEGRATION MODULE
÷2
BUS CLOCK
GENERATORS
SIMOSCEN
IT12
TO REST
OF MCU
IT23
TO REST
OF MCU
SIMDIV2
Figure 9-3. CGM Clock Signals
MONITOR MODE
USER MODE
PTC1
9.3.1 Bus Timing
In user mode, the internal bus frequency is either the oscillator output
(CGMXCLK) divided by four, CGMXCLK divided by two, or the PLL
output (CGMPCLK) divided by four.
9.3.2 Clock Start-up from POR or LVI Reset
When the power-on reset module or the low-voltage inhibit module
generates a reset, the clocks to the CPU and peripherals are inactive
and held in an inactive phase until after the 4096 ICLK cycle POR
timeout has completed. The RST pin is driven low by the SIM during this
entire period. The IBUS clocks start upon completion of the timeout.
MC68HC908LJ24/LK24 — Rev. 2.1
Freescale Semiconductor
System Integration Module (SIM)
Data Sheet
143