MC68HC908JB8 Datasheet, PDF (54/286 Pages) Motorola, Inc – MICROCONTROLLERS

FLASH Memory
Addr. Register Name
Bit 7
6
5
4
3
2
$FE08
FLASH Control Register ^Read:
(FLCR) _Write:
0
0
0
0
HVEN MASS
Reset: 0
0
0
0
0
0
$FE09
FLASH Block Protect Read:
Register
BPR7
(FLBPR) ^Write:
BPR6
BPR5
BPR4
BPR3
BPR2
Reset: 0
0
0
0
0
0
Figure 4-1. FLASH Memory Register Summary
1
ERASE
0
BPR1
0
Bit 0
PGM
0
BPR0
0
4.3 Functional Description
The FLASH memory consists of an array of 8,192 bytes for user memory
plus a small block of 16 bytes for user interrupt vectors. An erased bit
reads as logic 1 and a programmed bit reads as a logic 0. The FLASH
memory is block erasable. The minimum erase block size is 512 bytes.
Program and erase operation operations are facilitated through control
bits in FLASH control register (FLCR).The address ranges for the
FLASH memory are shown as follows:
• $DC00–$FBFF (user memory; 8,192 bytes)
• $FFF0–$FFFF (user interrupt vectors; 16 bytes)
NOTE:
Programming tools are available from Freescale. Contact your local
Freescale representative for more information.
A security feature prevents viewing of the FLASH contents.¹
Technical Data
54
1. No security feature is absolutely secure. However, Freescale’s strategy is to make reading or
copying the FLASH difficult for unauthorized users.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
FLASH Memory
Freescale Semiconductor