MC68HC908JB8 Datasheet, PDF (42/286 Pages) Motorola, Inc – MICROCONTROLLERS

Memory Map
Addr.
Register Name
Bit 7
6
5
$0000
Read:
Port A Data Register
(PTA)
Write:
Reset:
PTA7
PTA6
PTA5
$0001
Read:
Port B Data Register
(PTB)
Write:
Reset:
PTB7
PTB6
PTB5
$0002
Read:
Port C Data Register
(PTC)
Write:
Reset:
PTC7
PTC6
PTC5
$0003
Read:
Port D Data Register
(PTD)
Write:
Reset:
PTD7
PTD6
PTD5
Read:
$0004
Data Direction Register A
(DDRA)
Write:
Reset:
DDRA7
0*
DDRA6
0
DDRA5
0
* DDRA7 bit is reset by POR or LVI reset only.
Read:
$0005
Data Direction Register B
(DDRB)
Write:
Reset:
DDRB7
0
DDRB6
0
DDRB5
0
Read:
$0006
Data Direction Register C
(DDRC)
Write:
Reset:
DDRC7
0
DDRC6
0
DDRC5
0
Read:
$0007
Data Direction Register D
(DDRD)
Write:
Reset:
DDRD7
0
DDRD6
0
DDRD5
0
Read: 0
0
0
$0008
Port E Data Register
(PTE)
Write:
Reset:
Read: 0
0
0
$0009
Data Direction Register E
(DDRE)
Write:
Reset: 0
0
0
= Unimplemented
4
3
2
1
Bit 0
PTA4 PTA3 PTA2 PTA1 PTA0
Unaffected by reset
PTB4 PTB3 PTB2 PTB1 PTB0
Unaffected by reset
PTC4 PTC3 PTC2 PTC1 PTC0
Unaffected by reset
PTD4 PTD3 PTD2 PTD1 PTD0
Unaffected by reset
DDRA4 DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
DDRB4 DDRB3 DDRB2 DDRB1 DDRB0
0
0
0
0
0
DDRC4 DDRC3 DDRC2 DDRC1 DDRC0
0
0
0
0
0
DDRD4 DDRD3 DDRD2 DDRD1 DDRD0
0
0
0
0
0
PTE4 PTE3 PTE2 PTE1 PTE0
Unaffected by reset
DDRE4 DDRE3 DDRE2 DDRE1 DDRE0
0
0
0
0
0
R = Reserved
U = Unaffected by reset
Figure 2-2. Control, Status, and Data Registers (Sheet 1 of 8)
Technical Data
42
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Memory Map
Freescale Semiconductor