MC68HC908JB8 Datasheet, PDF (204/286 Pages) Motorola, Inc – MICROCONTROLLERS

Input/Output Ports (I/O)
When bit DDRAx is a logic 1, reading address $0000 reads the PTAx
data latch. When bit DDRAx is a logic 0, reading address $0000 reads
the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes
the operation of the port A pins.
Table 12-2. Port A Pin Functions
DDRA
Bit
0
1
PTA Bit
X⁽¹⁾
X
I/O Pin Mode
Accesses
to DDRA
Read/Write
Input, Hi-Z^{(2) DDRA[7:0]}
Output
DDRA[7:0]
Accesses to PTA
Read
Pin
PTA[7:0]
Write
PTA[7:0]⁽³⁾
PTA[7:0]
NOTES:
1. X = don’t care.
2. Hi-Z = high impedance.
3. Writing affects data register, but does not affect input.
12.4 Port B
Port B is an 8-bit general-purpose bidirectional I/O port with software
configurable pullups.
12.4.1 Port B Data Register
The port B data register contains a data latch for each of the eight port B
pins.
NOTE: PTB7–PTB0 are not available in the 20-pin PDIP, 20-pin SOIC, and
28-pin SOIC packages.
Address: $0001
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTB7
Write:
PTB6
PTB5
PTB4
PTB3
PTB2
PTB1
PTB0
Reset:
Unaffected by reset
Additional Optional Optional Optional Optional Optional Optional Optional Optional
Function: pullup pullup pullup pullup pullup pullup pullup pullup
Figure 12-5. Port B Data Register (PTB)
Technical Data
204
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor