MC68HC908JB8 Datasheet, PDF (166/286 Pages) Motorola, Inc – MICROCONTROLLERS

Monitor ROM (MON)
10.4.1 Entering Monitor Mode
Table 10-1 shows the pin conditions for entering monitor mode. As
specified in the table, monitor mode may be entered after a POR and will
allow communication at 9600 baud provided one of the following sets of
conditions is met:
1. If IRQ = V_DD + V_HI:
– External clock on OSC1 is 3MHz
– PTA3 = low
2. If IRQ = V_DD + V_HI:
– External clock on OSC1 is 6MHz
– PTA3 = high
3. If $FFFE & $FFFF is blank (contains $FF):
– External clock on OSC1 is 6MHz
– IRQ = V_DD
Table 10-1. Mode Entry Requirements and Options
External Clock,
f_XCLK
Bus
Frequency,
f_BUS
Comments
V_DD + V_HI
X
V_DD + V_HI
X
0011
1011
3 MHz
6 MHz
3 MHz
(f_XCLK)
3 MHz
(f_XCLK ÷ 2)
High-voltage entry to
monitor mode.
9600 baud communication
on PTA0. COP disabled.
BLANK
V_DD
(contain X X X 1
$FF)
6 MHz
3 MHz
(f_XCLK ÷ 2)
Low-voltage entry to
monitor mode.
9600 baud communication
on PTA0. COP disabled.
V_DD
NOT
BLANK
XXXX
6 MHz
3 MHz
(f_XCLK ÷ 2)
Enters user mode.
If $FFFE and $FFFF is
blank, MCU will encounter
an illegal address reset.
Notes:
1. PTA3 = 0: Bypasses the divide-by-two prescaler to SIM when using V_DD + V_HI for monitor mode entry.
2. See Section 18. Electrical Specifications for V_DD + V_HI voltage level requirements.
Technical Data
166
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Monitor ROM (MON)
Freescale Semiconductor