MC68HC908JB8 Datasheet, PDF (200/286 Pages) Motorola, Inc – MICROCONTROLLERS

Input/Output Ports (I/O)
NOTE:
Connect any unused I/O pins to an appropriate logic level, either V_REG
or V_SS. Although the I/O ports do not require termination for proper
operation, termination reduces excess current consumption and the
possibility of electrostatic damage.
Addr.
Register Name
Bit 7
6
5
$0000
Port A Data Register Read:
(PTA) _Write: ^PTA7
PTA6
PTA5
Reset:
$0001
Port B Data Register Read:
(PTB) _Write: ^PTB7
PTB6
PTB5
Reset:
$0002
Port C Data Register Read:
(PTC) _Write: ^PTC7
PTC6
PTC5
Reset:
$0003
Port D Data Register Read:
(PTD) _Write: ^PTD7
PTD6
PTD5
Reset:
$0004 Data Direction Register A Read:
(DDRA) _Write: ^{DDRA7 DDRA6 DDRA5}
Reset: 0*
0
0
* DDRA7 bit is reset by POR or LVI reset only.
$0005 Data Direction Register B Read:
(DDRB) _Write: ^{DDRB7 DDRB6 DDRB5}
Reset: 0
0
0
$0006 Data Direction Register C Read:
(DDRC) _Write: ^{DDRC7 DDRC6 DDRC5}
Reset: 0
0
0
$0007 Data Direction Register D Read:
(DDRD) _Write: ^{DDRD7 DDRD6 DDRD5}
Reset: 0
0
0
$0008 Port E Data Register Read: 0
0
0
(PTE) _Write:
Reset:
= Unimplemented
4
3
PTA4 PTA3
Unaffected by reset
PTB4 PTB3
Unaffected by reset
PTC4 PTC3
Unaffected by reset
PTD4 PTD3
Unaffected by reset
DDRA4 DDRA3
0
0
DDRB4 DDRB3
0
0
DDRC4 DDRC3
0
0
DDRD4 DDRD3
0
0
PTE4 PTE3
Unaffected by reset
2
PTA2
PTB2
PTC2
PTD2
DDRA2
0
DDRB2
0
DDRC2
0
DDRD2
0
PTE2
1
PTA1
PTB1
PTC1
PTD1
DDRA1
0
DDRB1
0
DDRC1
0
DDRD1
0
PTE1
Bit 0
PTA0
PTB0
PTC0
PTD0
DDRA0
0
DDRB0
0
DDRC0
0
DDRD0
0
PTE0
Figure 12-1. I/O Port Register Summary
Technical Data
200
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor