MC68HC908JB8 Datasheet, PDF (211/286 Pages) Motorola, Inc – MICROCONTROLLERS

Input/Output Ports (I/O)
Port D
12.6.2 Data Direction Register D
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
Address: $0007
Bit 7
6
5
4
3
2
1
Read:
DDRD7 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1
Write:
Reset: 0
0
0
0
0
0
0
Figure 12-12. Data Direction Register D (DDRD)
Bit 0
DDRD0
0
DDRD[7:0] — Data Direction Register D Bits
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
Port D pins are open-drain when configured as output.
NOTE: Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
NOTE:
For those devices packaged in a 20-pin PDIP and 20-pin SOIC package,
PTD7–PTD2 are not connected. DDRD7–DDRD2 should be set to a 1 to
configure PTD7–PTD2 as outputs.
For those devices packaged in a 28-pin SOIC package, PTD7 is not
connected. DDRD7 should be set to a 1 to configure PTD7 as output.
Figure 12-13 shows the port D I/O circuit logic.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Input/Output Ports (I/O)
Technical Data
211