MC68HC908JB8 Datasheet, PDF (246/286 Pages) Motorola, Inc – MICROCONTROLLERS

Break Module (BREAK)
17.3 Features
Features of the break module include the following:
• Accessible i/o registers during the break interrupt
• CPU-generated break interrupts
• Software-generated break interrupts
• COP disabling during break interrupts
17.4 Functional Description
When the internal address bus matches the value written in the break
address registers, the break module issues a breakpoint signal (BKPT)
to the SIM. The SIM then causes the CPU to load the instruction register
with a software interrupt instruction (SWI) after completion of the current
CPU instruction. The program counter vectors to $FFFC and $FFFD
($FEFC and $FEFD in monitor mode).
These events can cause a break interrupt to occur:
• A CPU-generated address (the address in the program counter)
matches the contents of the break address registers.
• Software writes a logic 1 to the BRKA bit in the break status and
control register.
When a CPU-generated address matches the contents of the break
address registers, the break interrupt begins after the CPU completes its
current instruction. A return-from-interrupt instruction (RTI) in the break
routine ends the break interrupt and returns the MCU to normal
operation. Figure 17-1 shows the structure of the break module.
Technical Data
246
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Break Module (BREAK)
Freescale Semiconductor