MC68HC908JB8 Datasheet, PDF (243/286 Pages) Motorola, Inc – MICROCONTROLLERS

Technical Data — MC68HC908JB8•MC68HC08JB8•MC68HC08JT8
Section 16. Low Voltage Inhibit (LVI)
16.1 Contents
16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243
16.3 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .243
16.4 LVI Control Register (CONFIG) . . . . . . . . . . . . . . . . . . . . . . .244
16.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 244
16.5.1 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.5.2 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .244
16.2 Introduction
This section describes the low-voltage inhibit module (LVI), which
monitors the voltage on the V_DD pin and generates a reset when the V_DD
voltage falls to the LVI trip (V_LVR) voltage.
16.3 Functional Description
Figure 16-1 shows the structure of the LVI module. The LVI is enabled
after a reset. The LVI module contains a bandgap reference circuit and
comparator. Setting LVI disable bit (LVID) disables the LVI to monitor
V_DD voltage.
The LVI module generates one output signal:
LVI Reset — an reset signal will be generated to reset the CPU when
V_DD drops to below the set trip point.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Low Voltage Inhibit (LVI)
Technical Data
243