MC68HC908JB8 Datasheet, PDF (251/286 Pages) Motorola, Inc – MICROCONTROLLERS

Break Module (BREAK)
Break Module Registers
Address: $FE00
Bit 7
6
5
4
3
2
1
Bit 0
Read:
SBSW
R
R
R
R
R
R
R
Write:
Note⁽¹⁾
Reset:
0
R = Reserved
1. Writing a logic zero clears SBSW.
Figure 17-6. Break Status Register (BSR)
SBSW — SIM Break Stop/Wait
This read/write bit is set when a break interrupt causes an exit from
wait or stop mode. Clear SBSW by writing a logic 0 to it. Reset clears
SBSW.
1 = Stop mode or wait mode was exited by break interrupt
0 = Stop mode or wait mode was not exited by break interrupt
SBSW can be read within the break state SWI routine. The user can
modify the return address on the stack by subtracting one from it. The
following code is an example of this.
This code works if the H register was stacked in the break interrupt
routine. Execute this code at the end of the break interrupt routine.
HIBYTE EQU 5
LOBYTE EQU 6
;
If not SBSW, do RTI
BRCLR SBSW,BSR, RETURN ; See if wait mode or stop mode
; was exited by break.
TST LOBYTE,SP
; If RETURNLO is not zero,
BNE DOLO
; then just decrement low byte.
DEC HIBYTE,SP
; Else deal with high byte, too.
DOLO DEC LOBYTE,SP
; Point to WAIT/STOP opcode.
RETURN PULH
RTI
; Restore H register.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Break Module (BREAK)
Technical Data
251