MC68HC908JB8 Datasheet, PDF (111/286 Pages) Motorola, Inc – MICROCONTROLLERS

System Integration Module (SIM)
Low-Power Modes
Wait mode can also be exited by a reset or break. A break interrupt
during wait mode sets the SIM break stop/wait bit, SBSW, in the break
status register (BSR). If the COP disable bit, COPD, in the mask option
register is logic 0, then the computer operating properly module (COP)
is enabled and remains active in wait mode.
IAB
WAIT ADDR
WAIT ADDR + 1
SAME
SAME
IDB
PREVIOUS DATA
NEXT OPCODE
SAME
SAME
R/W
NOTE: Previous data can be operand data or the WAIT opcode, depending on the
last instruction.
Figure 8-13. Wait Mode Entry Timing
Figure 8-14 and Figure 8-15 show the timing for WAIT recovery.
IAB
$6E0B
$6E0C $00FF $00FE $00FD $00FC
IDB $A6 $A6
$A6
$01
$0B
$6E
EXITSTOPWAIT
NOTE: EXITSTOPWAIT = RST pin or CPU interrupt or break interrupt
Figure 8-14. Wait Recovery from Interrupt or Break
IAB
$6E0B
32
CYCLES
32
CYCLES
RST VCT H RST VCT L
IDB $A6 $A6
$A6
RST
OSCXCLK
Figure 8-15. Wait Recovery from Internal Reset
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
System Integration Module (SIM)
Technical Data
111