MC68HC908JB8 Datasheet, PDF (238/286 Pages) Motorola, Inc – MICROCONTROLLERS

Computer Operating Properly (COP)
15.3 Functional Description
Figure 15-1 shows the structure of the COP module.
OSCXCLK
SIM
12-BIT SIM COUNTER
SIM RESET CIRCUIT
RESET STATUS REGISTER
INTERNAL RESET SOURCES⁽¹⁾
RESET VECTOR FETCH
COPCTL WRITE
COPEN (FROM SIM)
COPD (FROM CONFIG)
RESET
COPCTL WRITE
COP CLOCK
COP MODULE
6-BIT COP COUNTER
CLEAR
COP COUNTER
NOTE:
COP RATE SEL
(COPRS FROM CONFIG)
1. See SIM section for more details.
Figure 15-1. COP Block Diagram
The COP counter is a free-running 6-bit counter preceded by a 12-bit
system integration module (SIM) counter. If not cleared by software, the
COP counter overflows and generates an asynchronous reset after
2¹⁸ – 2⁴ or 2¹³ – 2⁴ OSCXCLK cycles, depending on the state of the
COP rate select bit, COPRS in the configuration register. With a 2¹⁸ – 2⁴
OSCXCLK cycle overflow option (COPRS = 0), a 12MHz OSCXCLK
clock (6MHz crystal) gives a COP timeout period of 21.84 ms. Writing
any value to location $FFFF before an overflow occurs prevents a COP
reset by clearing the COP counter and stages 12 through 5 of the SIM
counter.
Technical Data
238
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Computer Operating Properly (COP)
Freescale Semiconductor