MC68HC908JB8 Datasheet, PDF (189/286 Pages) Motorola, Inc – MICROCONTROLLERS

Timer Interface Module (TIM)
I/O Signals
11.9 I/O Signals
Port E shares three of its pins with the TIM. PTE0/TCLK is an external
clock input to the TIM prescaler. The two TIM channel I/O pins are
PTE1/TCH0 and PTE2/TCH1.
11.9.1 TIM Clock Pin (PTE0/TCLK)
PTE0/TCLK is an external clock input that can be the clock source for
the TIM counter instead of the prescaled internal bus clock. Select the
PTE0/TCLK input by writing logic 1s to the three prescaler select bits,
PS[2:0]. (See 11.10.1 TIM Status and Control Register.) The minimum
TCLK pulse width, TCLK_LMIN or TCLK_HMIN, is:
------------------1-------------------
bus frequency
+
t_SU
The maximum TCLK frequency is:
bus frequency ÷ 2
PTE0/TCLK is available as a general-purpose I/O pin when not used as
the TIM clock input. When the PTE0/TCLK pin is the TIM clock input, it
is an input regardless of the state of the DDRE0 bit in data direction
register E.
11.9.2 TIM Channel I/O Pins (PTE1/TCH0:PTE2/TCH1)
Each channel I/O pin is programmable independently as an input
capture pin or an output compare pin. PTE1/TCH0 can be configured as
buffered output compare or buffered PWM pins.
11.10 I/O Registers
The following I/O registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM counter registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Timer Interface Module (TIM)
Technical Data
189