MC68HC908JB8 Datasheet, PDF (167/286 Pages) Motorola, Inc – MICROCONTROLLERS

Monitor ROM (MON)
Functional Description
If V_DD +V_HI is applied to IRQ and PTA3 is low upon monitor mode entry
(Table 10-1 condition set 1), the bus frequency is a equal to the external
clock, f_XCLK. If PTA3 is high with V_DD +V_HI applied to IRQ upon monitor
mode entry (Table 10-1 condition set 2), the bus frequency is a divide-
by-two of the external clock. Holding the PTA3 pin low when entering
monitor mode causes a bypass of a divide-by-two stage at the oscillator
only if V_DD +V_HI is applied to IRQ. In this event, the OSCOUT frequency
is equal to the OSCXCLK frequency.
Entering monitor mode with V_DD + V_HI on IRQ, the COP is disabled as
long as V_DD + V_HI is applied to either the IRQ or the RST. (See Section
8. System Integration Module (SIM) for more information on modes of
operation.)
If entering monitor mode without high voltage on IRQ and reset vector
being blank ($FFFE and $FFFF) (Table 10-1 condition set 3, where IRQ
applied voltage is V_DD), then all port A pin requirements and conditions,
including the PTA3 frequency divisor selection, are not in effect. This is
to reduce circuit requirements when performing in-circuit programming.
Entering monitor mode with the reset vector being blank, the COP is
always disabled regardless of the state of IRQ or the RST.
Figure 10-2. shows a simplified diagram of the monitor mode entry when
the reset vector is blank and IRQ = V_DD. An external clock of 6MHz is
required for a baud rate of 9600.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Monitor ROM (MON)
Technical Data
167