MC68HC908JB8 Datasheet, PDF (239/286 Pages) Motorola, Inc – MICROCONTROLLERS

Computer Operating Properly (COP)
I/O Signals
NOTE:
Service the COP immediately after reset and before entering or after
exiting stop mode to guarantee the maximum time before the first COP
counter overflow.
A COP reset pulls the RST pin low for 32 OSCXCLK cycles and sets the
COP bit in the reset status register (RSR).
In monitor mode, the COP is disabled if the RST pin or the IRQ is held
at V_DD + V_HI. During the break state, V_DD + V_HI on the RST pin disables
the COP.
NOTE:
Place COP clearing instructions in the main program and not in an
interrupt subroutine. Such an interrupt subroutine could keep the COP
from generating a reset even while the main program is not working
properly.
15.4 I/O Signals
The following paragraphs describe the signals shown in Figure 15-1.
15.4.1 OSCXCLK
OSCXCLK is the clock doubler output signal. OSCXCLK frequency is
double of the crystal frequency.
15.4.2 STOP Instruction
The STOP instruction clears the COP prescaler.
15.4.3 COPCTL Write
Writing any value to the COP control register (COPCTL) (see 15.5 COP
Control Register) clears the COP counter and clears bits 12 through 5
of the SIM counter. Reading the COP control register returns the low
byte of the reset vector.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Computer Operating Properly (COP)
Technical Data
239