MC68HC908JB8 Datasheet, PDF (248/286 Pages) Motorola, Inc – MICROCONTROLLERS

Break Module (BREAK)
17.4.1 Flag Protection During Break Interrupts
The BCFE bit in the break flag control register (BFCR) enables software
to clear status bits during the break state.
17.4.2 CPU During Break Interrupts
The CPU starts a break interrupt by:
• Loading the instruction register with the SWI instruction
• Loading the program counter with $FFFC and $FFFD ($FEFC and
$FEFD in monitor mode)
The break interrupt begins after completion of the CPU instruction in
progress. If the break address register match occurs on the last cycle of
a CPU instruction, the break interrupt begins immediately.
17.4.3 TIM During Break Interrupts
A break interrupt stops the timer counter.
17.4.4 COP During Break Interrupts
The COP is disabled during a break interrupt when V_REG + V_HI is present
on the RST pin.
17.5 Low-Power Modes
The WAIT and STOP instructions put the MCU in low-power-
consumption standby modes.
17.5.1 Wait Mode
If enabled, the break module is active in wait mode. In the break routine,
the user can subtract one from the return address on the stack if SBSW
is set (see 8.7 Low-Power Modes). Clear the SBSW bit by writing logic
0 to it.
Technical Data
248
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Break Module (BREAK)
Freescale Semiconductor