MC68HC908JB8 Datasheet, PDF (210/286 Pages) Motorola, Inc – MICROCONTROLLERS

Input/Output Ports (I/O)
12.6.1 Port D Data Register
The port D data register contains a data latch for each of the eight port D
pins.
NOTE: PTD7–PTD2 are not available in the 20-pin PDIP and 20-pin SOIC
packages. PTD7 is not available in the 28-pin SOIC package.
Address: $0003
Bit 7
6
5
4
3
2
1
Bit 0
Read:
PTD7
Write:
PTD6
PTD5
PTD4
PTD3
PTD2
PTD1
PTD0
Reset:
Unaffected by reset
Additional Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain Open-drain
Function:
10mA 10mA 10mA 10mA 25mA 25mA
sink
sink
sink
sink
sink
sink
Figure 12-11. Port D Data Register (PTD)
PTD[7:0] — Port D Data Bits
These read/write bits are software programmable. Data direction of
each port D pin is under control of the corresponding bit in data
direction register D. Reset has no effect on port D data.
The LED direct drive bit, PTDLDD, in the port option control register
(POCR) controls the drive options for the PTD5–PTD2 pins. The
infrared LED drive bit, PTDILDD, in the POCR controls the drive
options for the PTD1–PTD0 pins. (See 12.8 Port Options.)
NOTE:
In 20-pin package, PTD1 and PTD0 are bonded together to PTD0/1 pin,
forming a 50mA high current sink pin. When both PTD1 and PTD0 are
configured as output, the values of PTD0 and PTD1 should be written
the same.
Technical Data
210
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Input/Output Ports (I/O)
Freescale Semiconductor