MC68HC908JB8 Datasheet, PDF (241/286 Pages) Motorola, Inc – MICROCONTROLLERS

Computer Operating Properly (COP)
COP Control Register
COPRS — COP Rate Select Bit
COPRS selects the COP timeout period. Reset clears COPRS.
1 = COP timeout period is (2¹³ – 2⁴) × OSCXOUT cycles
0 = COP timeout period is (2¹⁸ – 2⁴) × OSCXOUT cycles
COPD — COP Disable Bit
COPD disables the COP module.
1 = COP module disabled
0 = COP module enabled
15.5 COP Control Register
The COP control register is located at address $FFFF and overlaps the
reset vector. Writing any value to $FFFF clears the COP counter and
starts a new timeout period. Reading location $FFFF returns the low
byte of the reset vector.
Address: $FFFF
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Low byte of reset vector
Write:
Clear COP counter
Reset:
Unaffected by reset
Figure 15-3. COP Control Register (COPCTL)
15.6 Interrupts
The COP does not generate CPU interrupt requests.
15.7 Monitor Mode
The COP is disabled in monitor mode when V_DD + V_HI is present on the
IRQ pin or on the RST pin.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Computer Operating Properly (COP)
Technical Data
241