MC68HC908JB8 Datasheet, PDF (215/286 Pages) Motorola, Inc – MICROCONTROLLERS

Input/Output Ports (I/O)
Port E
12.7.2 Data Direction Register E
Data direction register E determines whether each port E pin is an input
or an output. Writing a logic 1 to a DDRE bit enables the output buffer for
the corresponding port E pin; a logic 0 disables the output buffer.
Address: $0009
Bit 7
6
5
4
3
2
1
Read: 0
0
0
DDRE4 DDRE3 DDRE2 DDRE1
Write:
Reset: 0
0
0
0
0
0
0
= Unimplemented
Figure 12-15. Data Direction Register E (DDRE)
Bit 0
DDRE0
0
DDRE[4:0] — Data Direction Register E Bits
These read/write bits control port E data direction. Reset clears
DDRE[4:0], configuring all port E pins as inputs.
1 = Corresponding port E pin configured as output
0 = Corresponding port E pin configured as input
PTE4 and PTE3 pins are open-drain when configured as output.
NOTE: Avoid glitches on port E pins by writing to the port E data register before
changing data direction register E bits from 0 to 1.
NOTE:
For those devices packaged in a 20-pin PDIP and 20-pin SOIC package,
PTE2 and PTE0 are not connected. DDRE2 and DDRE0 should be set
to a 1 to configure PTE2 and PTE0 as outputs.
Figure 12-16 shows the port E I/O circuit logic.
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Input/Output Ports (I/O)
Technical Data
215